PROJECTS
Design of Alarm Clock
A case study
04/2023 - 04/2023
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Design of an Alarm clock using Verilog HDL, Mentor Graphics
(ModelSim) & Quartus Prime.
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Employed the "block level" architecture to get the design. There are
6 sub blocks which are instantiated in the top module.
Design & Verification of Loadable Mod-12
Up-Down Counter
04/2023 - 04/2023
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In this Project, I designed and verified a counter which counts 12
numbers in up or down direction and starts counting from the
specified number in the specified direction when the load signal is
made high.
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The design is made using Verilog HDL and Verification is done using
SystemVerilog.
Router 1x3 Design
04/2023 - 04/2023
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A Router is a device that forwards data packets between computer
networks.
- I used 'block level' architecture.
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It has 6 sub blocks which include an FSM, a Synchronizer, a
Register and three FIFO blocks. In order to design the router, I
designed the sub blocks first and later instantiated those to
generate the "Router-Top" block.
Optimal Design of Microgrid System with Hybrid Renewable Energy
Resources Using Homer Pro
03/2022 - 06/2022
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In this project, we designed a microgrid system consisting of
renewable energy resources like solar and wind.
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We also considered alternate energy resources like the generator
and of course the main power grid.
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After integrating all the energy resources, we used the annual
load of GVPCE(A) for the power supply and observed the
energy consumption, emissions and other parameters like how much
power is sold to the grid.
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Conclusions were drawn based on the results to check whether the
system design is employable.